View LH28F800BG-L-FOR-SOP_1194701.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

- 1 - in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. lh28f800bg-l (for sop) 8 m-bit (512 kb x 16) smartvoltage flash memory lh28f800bg-l (for sop) description the lh28f800bg-l flash memory with smart voltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. the lh28f800bg-l can operate at v cc = 2.7 v and v pp = 2.7 v. its low voltage operation capability realizes longer battery life and suits for cellular phone application. its boot, parameter and main-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the lh28f800bg-l offers two levels of protection : absolute protection with v pp at gnd, selective hardware boot block locking. these alternatives give designers ultimate control of their code security needs. features ? smartvoltage technology C 2.7 v, 3.3 v or 5 v v cc C 2.7 v, 3.3 v, 5 v or 12 v v pp ? high performance read access time lh28f800bg-l85 C 85 ns (5.00.25 v)/90 ns (5.00.5 v)/ 100 ns (3.30.3 v)/120 ns (2.7 to 3.6 v) lh28f800bg-l12 C 120 ns (5.00.5 v)/130 ns (3.30.3 v)/ 150 ns (2.7 to 3.6 v) ? enhanced automated suspend options C word write suspend to read C block erase suspend to word write C block erase suspend to read ? enhanced data protection features C absolute protection with v pp = gnd C block erase/word write lockout during power transitions C boot blocks protection except rp# = v hh ? sram-compatible write interface ? optimized array blocking architecture C two 4 k-word boot blocks C six 4 k-word parameter blocks C fifteen 32 k-word main blocks C top or bottom boot location ? enhanced cycling capability C 100 000 block erase cycles ? low power management C deep power-down mode C automatic power saving mode decreases i cc in static mode ? automated word write and block erase C command user interface C status register ? etox tm * v nonvolatile flash technology ? package C 44-pin sop (sop044-p-0600) * etox is a trademark of intel corporation.
lh28f800bg-l (for sop) - 2 - pin connections 44-pin sop (sop044-p-0600) v pp a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce# gnd oe# dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 rp# we# a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 nc gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc comparison table * 1 refer to the datasheet of lh28f800bg-l/bgh-l (for tsop, csp). top view versions operating package dc characteristics write protect function temperature v cc deep power-down current (max.) for boot blocks lh28f800bg-l 0 to +70c 44-pin sop 10 a controlled by rp# pin (for sop) lh28f800bg-l * 1 0 to +70c 48-pin tsop (i) 10 a controlled by (for tsop, csp) 48-ball csp wp# and rp# pins lh28f800bgh-l * 1 C 40 to +85c 48-pin tsop (i) 20 a controlled by (for tsop, csp) 48-ball csp wp# and rp# pins
lh28f800bg-l (for sop) block organization this product features an asymmetrically-blocked architecture providing system memory integration. each erase block can be erased independently of the others up to 100 000 times. for the address locations of the blocks, see the memory map in fig. 1 . boot blocks : the two boot blocks are intended to replace a dedicated boot prom in a micro- processor or microcontroller-based system. the boot blocks of 4 k words (4 096 words) feature hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. the protection of the boot blocks is controlled using a combination of the v pp and rp# pins. parameter blocks : the boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an eeprom. by using software techniques, the byte-rewrite functionality of eeproms can be emulated. each boot block component contains six parameter blocks of 4 k words (4 096 words) each. the parameter blocks are not write-protectable. main blocks : the reminder is divided into main blocks for data or code storage. each 8 m-bit device contains fifteen 32 k words (32 768 words) blocks. - 3 - input buffer buffer output multiplexer v cc ce# rp# oe# identifier register command user interface write state machine program/erase voltage switch i/o logic status register data register data comparator 15 32 k-word main blocks x decoder y decoder y gating ry/by# v pp v cc gnd dq 0 -dq 15 a 0 -a 18 input buffer address latch address counter we# output boot block 0 boot block 1 parameter block 0 parameter block 1 parameter block 2 parameter block 3 parameter block 4 parameter block 5 main block 0 main block 1 main block 13 main block 14 block diagram
- 4 - lh28f800bg-l (for sop) symbol type name and function a 0 -a 18 input address inputs : inputs for addresses during read and write operations. addresses are internally latched during a write cycle. data input/outputs : inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. ce# input chip enable : activates the devices control logic, input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down : puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provide data protection during power transitions. exit from deep power-down sets the device to read array mode. with rp# = v hh , block erase or word write can operate to all blocks. block erase or word write with v ih < rp# < v hh produce spurious results and should not be attempted. oe# input output enable : gates the devices outputs during a read cycle. we# input write enable : controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. ready/busy : indicates the status of the internal wsm. when low, the wsm is performing an internal operation (block erase or word write). ry/by#-high indicates that the wsm is ready for new commands, block erase is suspended, and word write is inactive, word write is suspended, or the device is in deep power-down mode. ry/by# is always active and does not float when the chip is deselected or data outputs are disabled. v pp supply block erase and word write power supply : for erasing array blocks or writing words. with v pp v pplk , memory contents cannot be altered. block erase and word write with an invalid v pp (see section 6.2.3 "dc characteristics" ) produce spurious results and should not be attempted. device power supply : internal detection configures the device for 2.7 v, 3.3 v or 5 v operation. to switch from one voltage to another, ramp v cc down to gnd and then ramp v cc to the new voltage. do not float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see section 6.2.3 "dc characteristics" ) produce spurious results and should not be attempted. gnd supply ground : do not float any ground pins. nc no connect : lead is not internal connected; recommend to be floated. pin description dq 0 -dq 15 input/ output rp# input ry/by# output v cc supply
lh28f800bg-l (for sop) 1 introduction this datasheet contains lh28f800bg-l speci- fications. section 1 provides a flash memory overview. sections 2, 3, 4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. lh28f800bg-l flash memory documentation also includes ordering information which is referenced in section 7. 1.1 new features key enhancements of lh28f800bg-l smartvoltage flash memory are : ? smartvoltage technology ? enhanced suspend capabilities ? boot block architecture note following important differences : ?v pplk has been lowered to 1.5 v to support 2.7 v, 3.3 v and 5 v block erase and word write operations. designs that switch v pp off during read operations should make sure that the v pp voltage transitions to gnd. ? to take advantage of smartvoltage technology, allow v pp connection to 2.7 v, 3.3 v or 5 v. 1.2 product overview the lh28f800bg-l is a high-performance 8 m-bit smartvoltage flash memory organized as 512 k- word of 16 bits. the 512 k-word of data is arranged in two 4 k-word boot blocks, six 4 k-word parameter blocks and fifteen 32 k-word main blocks which are individually erasable in-system. the memory map is shown in fig. 1 . smartvoltage technology provides a choice of v cc and v pp combinations, as shown in table 1 , to meet system performance and power expectations. 2.7 v v cc consumes approximately one-fifth the power of 5 v v cc and 3.3 v v cc consumes approximately one-fourth the power of 5 v v cc . but, 5 v v cc provides the highest read performance. v pp at 2.7 v, 3.3 v and 5 v eliminates the need for a separate 12 v converter, while v pp = 12 v maximizes block erase and word write performance. in addition to flexible erase and program voltages, the dedicated v pp pin gives complete data protection when v pp v pplk . table 1 v cc and v pp voltage combinations offered by smartvoltage technology internal v cc and v pp detection circuitry auto- matically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and word write operations. a block erase operation erases one of the devices 32 k-word blocks typically within 0.39 second (5 v v cc , 12 v v pp ), 4 k-word blocks typically within 0.25 second (5 v v cc , 12 v v pp ) independent of other blocks. each block can be independently erased 100 000 times. block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. writing memory data is performed in word increments of the devices 32 k-word blocks typically within 8.4 s (5 v v cc , 12 v v pp ), 4 k-word blocks typically within 17 s (5 v v cc , 12 v v pp ). word write suspend mode enables the system to read data from, or write data to any other flash memory array location. v cc voltage v pp voltage 2.7 v 2.7 v, 3.3 v, 5 v, 12 v 3.3 v 3.3 v, 5 v, 12 v 5 v 5 v, 12 v - 5 -
- 6 - lh28f800bg-l (for sop) the boot block is located at either the top or the bottom of the address map in order to accommodate different micro-processor protect for boot code location. the hardware-lockable boot block provides complete code security for the kernel code required for system initialization. locking and unlocking of the boot block is controlled by rp# (see section 4.9 for details). block erase or word write for boot block must not be carried out by rp# to v ih . the status register indicates when the wsms block erase or word write operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is performing a block erase or word write. ry/by#-high indicates that the wsm is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep power-down mode. the access time is 85 ns (t avqv ) at the v cc supply voltage range of 4.75 to 5.25 v over the temperature range (0 to +70c). at 4.5 to 5.5 v v cc , the access time is 90 ns or 120 ns. at lower v cc voltage, the access time is 100 ns or 130 ns (3.0 to 3.6 v) and 120 ns or 150 ns (2.7 to 3.6 v). the automatic power saving (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 1 ma at 5 v v cc and 3 ma at 2.7 v and 3.3 v v cc . when ce# and rp# pins are at v cc , the i cc cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared.
lh28f800bg-l (for sop) - 7 - 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 7ffff 78000 77fff 6ffff 70000 68000 67fff 60000 5ffff 58000 57fff 50000 4ffff 48000 47fff 40000 3ffff 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 07000 06fff 06000 05fff 05000 04fff 04000 03fff 03000 02fff 02000 01fff 01000 00fff 00000 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 k-word parameter block 5 4 k-word parameter block 4 4 k-word parameter block 3 4 k-word parameter block 2 4 k-word parameter block 1 4 k-word parameter block 0 4 k-word boot block 1 4 k-word boot block 0 bottom boot 4 k-word boot block 4 k-word boot block 4 k-word parameter block 4 k-word parameter block 4 k-word parameter block 4 k-word parameter block 4 k-word parameter block 4 k-word parameter block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 32 k-word main block 7ffff 7f000 7efff 7dfff 7e000 7d000 7cfff 7c000 7bfff 7b000 7afff 7a000 79fff 79000 78fff 78000 77fff 70000 6ffff 68000 67fff 60000 5ffff 58000 57fff 50000 4ffff 48000 47fff 40000 3ffff 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 00000 0 1 0 1 2 3 4 5 0 1 2 3 4 5 6 32 k-word main block 7 32 k-word main block 8 32 k-word main block 9 32 k-word main block 10 32 k-word main block 11 32 k-word main block 12 32 k-word main block 13 32 k-word main block 14 top boot fig. 1 memory map block configuration versions top boot lh28f800bg-tl bottom boot lh28f800bg-bl notes :
lh28f800bg-l (for sop) 2 principles of operation the lh28f800bg-l smartvoltage flash memory includes an on-chip wsm to manage block erase and word write functions. it allows for : 100% ttl- level control inputs, fixed power supplies during block erasure and word write, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see table 2 "bus operations" ), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erasure and word writing. all functions associated with altering memory contentsblock erase, word write, status and identifier codesare accessed via the cui and verified through the status register. commands are written using standard micro- processor write timings. the cui contents serve as input to the wsm, which controls the block erase and word write. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. interface software that initiates and polls progress of block erase and word write can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. word write suspend allows system software to suspend a word write to read data from any other flash memory array location. 2.1 data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when memory block erases or word writes are required) or hardwired to v pph1/2/3 . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. the cui, with two-step block erase or word write command sequences, provides protection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v cc is below the write lockout voltage v lko or when rp# is at v il . the devices boot blocks locking capability for rp# provides additional protection from inadvertent code or data alteration by block erase and word write operations. refer to table 5 for write protection alternatives. 3 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes or status register independent of the v pp voltage. rp# can be at either v ih or v hh . the first task is to write the appropriate read mode command (read array, read identifier codes or read status register) to the cui. upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read array mode. four control pins dictate the data flow in and out of the component : ce#, oe#, we# and rp#. ce# and oe# must be driven active to obtain - 8 -
- 9 - lh28f800bg-l (for sop) data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 -dq 15 ) control and when active drives the selected memory data onto the i/o bus. we# must be at v ih and rp# must be at v ih or v hh . fig. 11 illustrates read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins (dq 0 -dq 15 ) are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 -dq 15 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase or word write, the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of 100 ns. time t phqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase or word write modes, rp#-low will abort the operation. ry/by# remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase or word write modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharps flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 3.5 read identifier codes operation the read identifier codes operation outputs the manufacture code and device code (see fig. 2 ). using the manufacture and device codes, the system cpu can automatically match the device with its proper algorithms. fig. 2 device identifier code memory map 3.6 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v cc = v cc1/2/3/4 and v pp = v pph1/2/3 , the cui additionally controls block erasure and word write. the block erase command requires appropriate command data and an address within the block to be erased. the word write command requires the 7ffff 00002 00001 00000 reserved for future implementation device code manufacture code
- 10 - lh28f800bg-l (for sop) command and address of the location to be written. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. fig. 12 and fig. 13 illustrate we# and ce# controlled write operations. 4 command definitions when the v pp voltage v pplk , read operations from the status register, identifier codes, or blocks are enabled. placing v pph1/2/3 on v pp enables successful block erase and word write operations. device operations are selected by writing specific commands into the cui. table 3 defines these commands. table 2 bus operations mode note rp# ce# oe# we# address v pp dq 0-15 ry/by# read 1, 2, 3, 8 v ih or v hh v il v il v ih xxd out x output disable 3 v ih or v hh v il v ih v ih x x high z x standby 3 v ih or v hh v ih xxxx high z x deep power-down 4 v il xxxxx high z v oh read identifier codes 8 v ih or v hh v il v il v ih see fig. 2 x( note 5) v oh write 3, 6, 7, 8 v ih or v hh v il v ih v il xxd in x notes : 1. refer to section 6.2.3 "dc characteristics" . when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2/3 for v pp . see section 6.2.3 "dc characteristics" for v pplk and v pph1/2/3 voltages. 3. ry/by# is v ol when the wsm is executing internal block erase or word write algorithms. it is v oh during when the wsm is not busy, in block erase suspend mode (with word write inactive), word write suspend mode or deep power-down mode. 4. rp# at gnd0.2 v ensures the lowest deep power- down current. 5. see section 4.2 for read identifier code data. 6. command writes involving block erase or word write are reliably executed when v pp = v pph1/2/3 and v cc = v cc1/2/3/4 . block erase or word write with v ih < rp# < v hh produce spurious results and should not be attempted. 7. refer to table 3 for valid d in during a write operation. 8. dont use the timing both oe# and we# are v il .
lh28f800bg-l (for sop) - 11 - command bus cycles note first bus cycle second bus cycle req d. oper (note 1) addr (note 2) data (note 3) oper (note 1) addr (note 2) data (note 3) read array/reset 1 write x ffh read identifier codes 3 2 4 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write ba 20h write ba d0h word write 2 5, 6 write wa 40h or 10h write wa wd block erase and 1 5 write x b0h word write suspend block erase and 1 5 write x d0h word write resume table 3 command definitions (note 7) notes : 1. bus operations are defined in table 2 . 2. x = any valid address within the device. ia = identifier code address : see fig. 2 . ba = address within the block being erased. wa = address of memory location to be written. 3. srd = data read from status register. see table 6 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. 4. following the read identifier codes command, read operations access manufacture and device codes. see section 4.2 for read identifier code data. 5. if the block is boot block, rp# must be at v hh to enable block erase or word write operations. attempts to issue a block erase or word write to a boot block while rp# is v ih . 6. either 40h or 10h is recognized by the wsm as the word write setup. 7. commands other than those shown above are reserved by sharp for future device implementations and should not be used.
- 12 - lh28f800bg-l (for sop) 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or word write, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or word write suspend command. the read array command functions independently of the v pp voltage and rp# can be v ih or v hh . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in fig. 2 retrieve the manufacture and device codes (see table 4 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage and rp# can be v ih or v hh . following the read identifier codes command, the following information can be read : table 4 identifier codes 4.3 read status register command the status register may be read to determine when a block erase or word write is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage. rp# can be v ih or v hh . 4.4 clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 6 ). by allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pp voltage. rp# can be v ih or v hh . this command is not functional during block erase or word write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by a block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see fig. 3 ). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. code address data manufacture code 00000h 00b0h device code (top boot) 00001h 0060h device code (bottom boot) 00001h 0062h
- 13 - lh28f800bg-l (for sop) the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v cc = v cc1/2/3/4 and v pp = v pph1/2/3 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". successful block erase for boot blocks requires that the corresponding if set, that rp# = v hh . if block erase is attempted to boot block when the corresponding rp#=v ih , sr.1 and sr.5 will be set to "1". block erase operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.6 word write command word write is executed by a two-cycle command sequence. word write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word write and write verify algorithms internally. after the word write sequence is written, the device automatically outputs status register data when read (see fig. 4 ). the cpu can detect the completion of the word write event by analyzing the ry/by# pin or status register bit sr.7. when word write is complete, status register bit sr.4 should be checked. if word write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the cui remains in read status register mode until it receives another command. reliable word writes can only occur when v cc = v cc1/2/3/4 and v pp = v pph1/2/3 . in the absence of this high voltage, memory contents are protected against word writes. if word write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful word write for boot blocks requires that the corresponding if set, that rp# = v hh . if word write is attempted to boot block when the corresponding rp# = v ih , sr.1 and sr.4 will be set to "1". word write operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.7 block erase suspend command the block erase suspend command allows block erase interruption to read or word write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to "1"). ry/by# will also transition to v oh. specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a word write command sequence can also be issued during erase suspend to program data in other blocks. using the word write suspend command (see section 4.8 ), a word write operation can also be suspended. during a word write operation with block erase suspended, status register bit sr.7 will return to "0" and the ry/by# output will transition to v ol . however, sr.6 will remain "1" to indicate block erase suspend status.
- 14 - lh28f800bg-l (for sop) the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/by# will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see fig. 5 ). v pp must remain at v pph1/2/3 (the same v pp level used for block erase) while block erase is suspended. rp# must also remain at v ih or v hh (the same rp# level used for block erase). block erase cannot resume until word write operations initiated during block erase suspend have completed. 4.8 word write suspend command the word write suspend command allows word write interruption to read data in other flash memory locations. once the word write process starts, writing the word write suspend command requests that the wsm suspend the word write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the word write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the word write operation has been suspended (both will be set to "1"). ry/by# will also transition to v oh . specification t whrh1 defines the word write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while word write is suspended are read status register and word write resume. after word write resume command is written to the flash memory, the wsm will continue the word write process. status register bits sr.2 and sr.7 will automatically clear and ry/by# will return to v ol . after the word write resume command is written, the device automatically outputs status register data when read (see fig. 6 ). v pp must remain at v pph1/2/3 (the same v pp level used for word write) while in word write suspend mode. rp# must also remain at v ih or v hh (the same rp# level used for word write). 4.9 block locking this boot block flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. 4.9.1 v pp = v il for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. 4.9.2 block unlocking rp# = v hh unlocks all lockable blocks. these blocks can now be programmed or erased. rp# controls all block locking and v pp provides protection against spurious writes. table 5 defines the write protection methods. table 5 write protection alternatives operation v pp rp# effect block erase v il x all blocks locked. or v il all blocks locked. word write > v pplk v ih 2 boot blocks locked. v hh all blocks unlocked.
- 15 - lh28f800bg-l (for sop) table 6 status register definition wsms ess es wws vpps wwss dps r 76543210 sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase status (es) 1 = error in block erase 0 = successful block erase sr.4 = word write status (wws) 1 = error in word write 0 = successful word write sr.3 = v pp status (vpps) 1=v pp low detect, operation abort 0=v pp ok sr.2 = word write suspend status (wwss) 1 = word write suspended 0 = word write in progress/completed sr.1 = device protect status (dps) 1 = rp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes : check ry/by# or sr.7 to determine block erase or word write completion. sr.6-0 are invalid while sr.7 = " 0 " . if both sr.5 and sr.4 are " 1 " s after a block erase attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase or word write command sequences. sr.3 is not guaranteed to reports accurate feedback only when v pp 1 v pph1/2/3 . the wsm interrogates the rp# only after block erase or word write command sequences. it informs the system, depending on the attempted operation, if the rp# is not v hh . sr.0 is reserved for future use and should be masked out when polling the status register.
lh28f800bg-l (for sop) - 16 - block erase complete start write 20h, block address write d0h, block address read status register 0 sr.7 = 1 full status check if desired repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last block erase operation to place device in read array mode. bus operation write write read standby command erase setup comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect check sr.5 1 = block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. no suspend block erase yes suspend block erase loop erase confirm block erase successful sr.4, 5 = command sequence error 1 0 sr.5 = block erase error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error fig. 3 automated block erase flowchart
lh28f800bg-l (for sop) - 17 - word write complete start write 40h or 10h, address write word data and address read status register 0 sr.7 = 1 full status check if desired repeat for subsequent word writes. sr full status check can be done after each word write or after a sequence of word writes. write ffh after the last word write operation to place device in read array mode. bus operation write write read standby command setup word write comments data = 40h or 10h addr = location to be written data = data to be written addr = location to be written status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby check sr.1 1 = device protect detect sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. no suspend word write yes suspend word write loop word write word write successful sr.4 = word write error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4 1 = data write error fig. 4 automated word write flowchart
lh28f800bg-l (for sop) - 18 - block erase resumed start write b0h read status register 0 sr.7 = 1 word write bus operation write read standby standby command erase suspend comments data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = block erase suspended 0 = block erase completed erase resume sr.6 = write d0h done? block erase completed write ffh read array data 1 0 no yes write data = d0h addr = x read or word write? read read array data word write loop fig. 5 block erase suspend/resume flowchart
lh28f800bg-l (for sop) - 19 - word write resumed start write b0h read status register 0 sr.7 = 1 write ffh bus operation write read standby standby command word write suspend comments data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = word write suspended 0 = word write completed read array sr.2 = read array data done reading write d0h word write completed write ffh read array data 1 0 no yes write read write word write resume data = ffh addr = x read array locations other than that being written. data = d0h addr = x fig. 6 word write suspend/resume flowchart
lh28f800bg-l (for sop) 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three- line control provides for : a. lowest possible memory power consumption. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by#, block erase and word write polling ry/by# is a full cmos output that provides a hardware method of detecting block erase and word write completion. it transitions low after block erase or word write commands and returns to v oh when the wsm has finished executing the internal algorithm. ry/by# can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/by# is also v oh when the device is in block erase suspend (with word write inactive), word write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the arrays power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for word writing and block erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 5.5 v cc , v pp , rp# transitions block erase and word write are not guaranteed if v pp falls outside of a valid v pph1/2/3 range, v cc falls outside of a valid v cc1/2/3/4 range, or rp# v ih or v hh . if v pp error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase or word write, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v il clear the status register. - 20 -
- 21 - lh28f800bg-l (for sop) the cui latches commands issued by system software and is not altered by v pp or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power- down or after v cc transitions below v lko . after block erase or word write, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against accidental block erasure or word writing during power transitions. upon power-up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the cuis two-step command sequence architecture provides added level of protection against data alteration. rp# provide additional protection from inadvertent code or data alteration. the device is disabled while rp# = v il regardless of its control inputs state. 5.7 power consumption when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memorys nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications that use an array of devices for solid- state storage can consume negligible power by lowering rp# to v il standby or sleep modes. if access is again needed, the devices can be read following the t phqv and t phwl wake-up cycles required after rp# is first raised to v ih . see section 6.2.4 through 6.2.6 "ac characteristics - read-only and write operations" and fig. 11 , fig. 12 and fig.13 for more information.
- 22 - lh28f800bg-l (for sop) 6 electrical specifications 6.1 absolute maximum ratings * operating temperature during read, block erase and word write ............................. 0 to +70c (note 1) temperature under bias ............. C 10 to +80c storage temperature ........................ C 65 to +125c voltage on any pin (except v cc , v pp , and rp#) .... C 2.0 to +7.0 v (note 2) v cc supply voltage ................. C 2.0 to +7.0 v (note 2) v pp update voltage during block erase and word write .................. C 2.0 to +14.0 v (note 2, 3) rp# voltage ........................ C 2.0 to +14.0 v (note 2, 3) output short circuit current ............... 100 ma (note 4) * warning : stressing the device beyond the " absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes : 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is C 0.5 v on input/output pins and C 0.2 v on v cc and v pp pins. during transitions, this level may undershoot to C 2.0 v for periods < 20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods < 20 ns. 3. maximum dc voltage on v pp and rp# may overshoot to +14.0 v for periods < 20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. notice : the specifications are subject to change without notice. verify with your local sharp sales office that you have the latest datasheet before finalizing a design. symbol parameter note min. max. unit version t a operating temperature 1 0 +70 ? c v cc1 v cc supply voltage (2.7 to 3.6 v) 2.7 3.6 v v cc2 v cc supply voltage (3.30.3 v) 3.0 3.6 v v cc3 v cc supply voltage (5.00.25 v) 4.75 5.25 v lh28f800bg-l85 v cc4 v cc supply voltage (5.00.5 v) 4.50 5.50 v 6.2 operating conditions note : 1. test condition : ambient temperature
lh28f800bg-l (for sop) - 23 - 6.2.2 ac input/output test conditions test points input output 1.35 1.35 2.7 0.0 fig. 7 transient input/output reference waveform for v cc = 2.7 to 3.6 v 1.5 1.5 3.0 0.0 test points input output fig. 8 transient input/output reference waveform for v cc = 3.3 0.3 v and v cc = 5.00.25 v (high speed testing configuration) ac test inputs are driven at 2.7 v for a logic "1" and 0.0 v for a logic "0". input timing begins, and output timing ends, at 1.35 v. input rise and fall times (10% to 90%) < 10 ns. ac test inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0". input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. 2.0 0.8 2.0 0.8 2.4 0.45 test points input output fig. 9 transient input/output reference waveform for v cc = 5.0 0.5 v (standard testing configuration) ac test inputs are driven at v oh (2.4 v ttl ) for a logic "1" and v ol (0.45 v ttl ) for a logic "0". input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. note : 1. sampled, not 100% tested. symbol parameter typ. max. unit condition c in input capacitance 7 10 pf v in = 0.0 v c out output capacitance 9 12 pf v out = 0.0 v 6.2.1 capacitance (note 1) t a = +25 ? c, f = 1 mhz
lh28f800bg-l (for sop) - 24 - device under test c l includes jig capacitance r l = 3.3 k w c l out 1.3 v 1n914 fig. 10 transient equivalent testing load circuit test configuration c l (pf) v cc = 3.30.3 v, 2.7 to 3.6 v 50 v cc = 5.00.25 v (note 1) 30 v cc = 5.00.5 v 100 test configuration capacitance loading value note : 1. applied to high-speed product, lh28f800bg-l85.
- 25 - symbol parameter note v cc = 2.7 to 3.6 v v cc = 5.00.5 v unit test typ. max. typ. max. conditions i li input load current 1 0.5 1 a v cc = v cc max. v in = v cc or gnd i lo output leakage current 1 0.5 10 a v cc = v cc max. v out = v cc or gnd cmos inputs 25 50 30 100 a v cc = v cc max. i ccs v cc standby current 1, 3, 6 ce# = rp# = v cc 0.2 v ttl inputs 0.2 2 0.4 2 ma v cc = v cc max. ce# = rp# = v ih i ccd v cc deep power-down 1 4 10 10 a rp# = gnd0.2 v current i out (ry/by#) = 0 ma cmos inputs v cc = v cc max. 15 25 50 ma ce# = gnd f = 5 mhz (3.3 v, 2.7 v), 8 mhz (5 v) i ccr v cc read current 1, 5, 6 i out = 0 ma ttl inputs v cc = v cc max. 30 65 ma ce# = gnd f = 5 mhz (3.3 v, 2.7 v), 8 mhz (5 v) i out = 0 ma 517mav pp = 2.7 to 3.6 v i ccw v cc word write current 1, 7 5 17 35 ma v pp = 5.00.5 v 512 30mav pp = 12.00.6 v 417mav pp = 2.7 to 3.6 v i cce v cc block erase current 1, 7 4 17 30 ma v pp = 5.00.5 v 412 25mav pp = 12.00.6 v i ccws v cc word write or block 1, 2 1 6 1 10 ma ce# = v ih i cces erase suspend current i pps v pp standby or read current 1 2 15 2 15 a v pp v cc i ppr 10 200 10 200 a v pp > v cc i ppd v pp deep power-down 1 0.1 5 0.1 5 a rp# = gnd0.2 v current 12 40 ma v pp = 2.7 to 3.6 v i ppw v pp word write current 1, 7 40 40 ma v pp = 5.00.5 v 30 30 ma v pp = 12.00.6 v 825mav pp = 2.7 to 3.6 v i ppe v pp block erase current 1, 7 25 25 ma v pp = 5.00.5 v 20 20 ma v pp = 12.00.6 v i ppws v pp word write or block 1 10 200 10 200 a v pp = v pph1/2/3 i ppes erase suspend current lh28f800bg-l (for sop) 6.2.3 dc characteristics
- 26 - symbol parameter note v cc = 2.7 to 3.6 v v cc = 5.00.5 v unit test min. max. min. max. conditions v il input low voltage 7 C 0.5 0.8 C 0.5 0.8 v v ih input high voltage 7 2.0 v cc 2.0 v cc v +0.5 +0.5 v cc = v cc min. v ol output low voltage 3, 7 0.4 0.45 v i ol = 5.8 ma (5 v) i ol = 2.0 ma (3.3 v, 2.7 v) output high voltage v cc = v cc min. v oh1 (ttl) 3, 7 2.4 2.4 v i oh = C 2.5 ma (5 v) i oh = C 2.0 ma (3.3 v, 2.7 v) 0.85 0.85 v v cc = v cc min. v oh2 output high voltage 3, 7 v cc v cc i oh = C 2.5 ma (cmos) v cc v cc v v cc = v cc min. C 0.4 C 0.4 i oh = C 100 a v pplk v pp lockout voltage during 4, 7 1.5 1.5 v normal operations v pph1 v pp voltage during word write 2.7 3.6 v or block erase operations v pph2 v pp voltage during word write 4.5 5.5 4.5 5.5 v or block erase operations v pph3 v pp voltage during word write 11.4 12.6 11.4 12.6 v or block erase operations v lko v cc lockout voltage 2.0 2.0 v v hh rp# unlock voltage 8, 9 11.4 12.6 11.4 12.6 v unlock boot blocks lh28f800bg-l (for sop) 6.2.3 dc characteristics (contd.) notes : 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25?c. these currents are valid for all product versions (packages and speeds). 2. i ccws and i cces are specified with the device de- selected. if reading or word writing in erase suspend mode, the devices current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes ry/by#. 4. block erases and word writes are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.), between v pph2 (max.) and v pph3 (min.), and above v pph3 (max.). 5. automatic power saving (aps) reduces typical i ccr to 1 ma at 5 v v cc and 3 ma at 2.7 v and 3.3 v v cc in static operation. 6. cmos inputs are either v cc 0.2 v or gnd0.2 v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. 8. boot block erases and word writes are inhibited when the corresponding rp# = v ih . block erase and word write operations are not guaranteed with v ih < rp# < v hh and should not be attempted. 9. rp# connection to a v hh supply is allowed for a maximum cumulative period of 80 hours.
lh28f800bg-l (for sop) - 27 - 6.2.4 ac characteristics - read-only operations (note 1) ? v cc = 2.7 to 3.6 v, t a = 0 to +70 ? c versions lh28f800bg-l85 lh28f800bg-l12 unit symbol parameter note min. max. min. max. t avav read cycle time 120 150 ns t avqv address to output delay 120 150 ns t elqv ce# to output delay 2 120 150 ns t phqv rp# high to output delay 600 600 ns t glqv oe# to output delay 2 50 55 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# high to output in high z 3 55 55 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# high to output in high z 3 20 25 ns t oh output hold from address, ce# or 3 0 0 ns oe# change, whichever occurs first versions lh28f800bg-l85 lh28f800bg-l12 unit symbol parameter note min. max. min. max. t avav read cycle time 100 130 ns t avqv address to output delay 100 130 ns t elqv ce# to output delay 2 100 130 ns t phqv rp# high to output delay 600 600 ns t glqv oe# to output delay 2 50 55 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# high to output in high z 3 55 55 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# high to output in high z 3 20 25 ns t oh output hold from address, ce# or 30 0 ns oe# change, whichever occurs first notes : 1. see ac input/output reference waveform ( fig. 7 through fig. 9 ) for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. ?v cc = 3.30.3 v, t a = 0 to +70?c
- 28 - symbol parameter note min. max. min. max. min. max. t avav read cycle time 85 90 120 ns t avqv address to output delay 85 90 120 ns t elqv ce# to output delay 2 85 90 120 ns t phqv rp# high to output delay 400 400 400 ns t glqv oe# to output delay 2 40 45 50 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# high to output in high z 3 55 55 55 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# high to output in high z 3 10 10 15 ns output hold from address, t oh ce# or oe# change, 3 0 0 0 ns whichever occurs first lh28f800bg-l (for sop) versions v cc 0.25 v v cc 0.5 v (note 4) lh28f800bg-l85 (note 5) lh28f800bg-l12 (note 5) lh28f800bg-l85 unit notes : 1. see ac input/output reference waveform ( fig. 7 through fig. 9 ) for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. see fig. 8 "transient input/output reference waveform" and fig. 10 "transient equivalent testing load circuit" (high speed configuration) for testing characteristics. 5. see fig. 9 "transient input/output reference waveform" and fig. 10 "transient equivalent testing load circuit" (standard configuration) for testing characteristics. 6.2.4 ac characteristics - read-only operations (contd.) (note 1) ?v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c
lh28f800bg-l (for sop) - 29 - addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) v cc standby device address selection data valid address stable t avav t ehqz t ghqz high z valid output t glqv t elqv t glqx t elqx t avqv t phqv high z v il v oh v ol v ih v ih v ih v ih v ih v il v il v il v il (dq 0 -dq 15 ) t oh fig. 11 ac waveform for read operations
lh28f800bg-l (for sop) - 30 - 6.2.5 ac characteristics - write operations (note 1) ? v cc = 2.7 to 3.6 v, t a = 0 to +70 ? c versions lh28f800bg-l85 lh28f800bg-l12 unit symbol parameter note min. max. min. max. t avav write cycle time 120 150 ns t phwl rp# high recovery to we# going low 2 1 1 s t elwl ce# setup to we# going low 10 10 ns t wlwh we# pulse width 50 50 ns t phhwh rp# v hh setup to we# going high 2 100 100 ns t vpwh v pp setup to we# going high 2 100 100 ns t avwh address setup to we# going high 3 50 50 ns t dvwh data setup to we# going high 3 50 50 ns t whdx data hold from we# high 5 5 ns t whax address hold from we# high 5 5 ns t wheh ce# hold from we# high 10 10 ns t whwl we# pulse width high 30 30 ns t whrl we# high to ry/by# going low 100 100 ns t whgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, ry/by# high 2, 4 0 0 ns t qvph rp# v hh hold from valid srd, ry/by# high 2, 4 0 0 ns versions lh28f800bg-l85 lh28f800bg-l12 unit symbol parameter note min. max. min. max. t avav write cycle time 100 130 ns t phwl rp# high recovery to we# going low 2 1 1 s t elwl ce# setup to we# going low 10 10 ns t wlwh we# pulse width 50 50 ns t phhwh rp# v hh setup to we# going high 2 100 100 ns t vpwh v pp setup to we# going high 2 100 100 ns t avwh address setup to we# going high 3 50 50 ns t dvwh data setup to we# going high 3 50 50 ns t whdx data hold from we# high 5 5 ns t whax address hold from we# high 5 5 ns t wheh ce# hold from we# high 10 10 ns t whwl we# pulse width high 30 30 ns t whrl we# high to ry/by# going low 100 100 ns t whgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, ry/by# high 2, 4 0 0 ns t qvph rp# v hh hold from valid srd, ry/by# high 2, 4 0 0 ns ?v cc = 3.30.3 v, t a = 0 to +70 ? c notes : 1. read timing characteristics during block erase and word write operations are the same as during read-only operations. refer to section 6.2.4 "ac charac- teristics" for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase or word write. 4. v pp should be held at v pph1/2/3 (and if necessary rp# should be held at v hh ) until determination of block erase or word write success (sr.1/3/4/5 = 0 : on boot blocks, sr.3/4/5 = 0 : on parameter blocks and main blocks).
notes : 1. read timing characteristics during block erase and word write operations are the same as during read-only operations. refer to section 6.2.4 "ac charac- teristics" for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase or word write. 4. v pp should be held at v pph1/2/3 (and if necessary rp# should be held at v hh ) until determination of block erase or word write success (sr.1/3/4/5 = 0 : on boot blocks, sr.3/4/5 = 0 : on parameter blocks and main blocks). 5. see fig. 8 "transient input/output reference waveform" and fig. 10 "transient equivalent testing load circuit" (high seed configuration) for testing characteristics. 6. see fig. 9 "transient input/output reference waveform" and fig. 10 "transient equivalent testing load circuit" (standard configuration) for testing characteristics. symbol parameter note min. max. min. max. min. max. t avav write cycle time 85 90 120 ns t phwl rp# high recovery to we# 2111s going low t elwl ce# setup to we# going low 10 10 10 ns t wlwh we# pulse width 40 40 40 ns t phhwh rp# v hh setup to we# going high 2 100 100 100 ns t vpwh v pp setup to we# going high 2 100 100 100 ns t avwh address setup to we# going high 3404040ns t dvwh data setup to we# going high 3 40 40 40 ns t whdx data hold from we# high 5 5 5 ns t whax address hold from we# high 5 5 5 ns t wheh ce# hold from we# high 10 10 10 ns t whwl we# pulse width high 30 30 30 ns t whrl we# high to ry/by# going low 90 90 90 ns t whgl write recovery before read 0 0 0 ns t qvvl v pp hold from valid srd, 2, 4 0 0 0 ns ry/by# high t qvph rp# v hh hold from valid srd, 2, 4 0 0 0 ns ry/by# high versions v cc 0.25 v v cc 0.5 v (note 5) lh28f800bg-l85 (note 6) lh28f800bg-l12 (note 6) lh28f800bg-l85 unit lh28f800bg-l (for sop) - 31 - 6.2.5 ac characteristics - write operations (contd.) (note 1) ?v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c
lh28f800bg-l (for sop) - 32 - v il v ih v oh v ih v ih v ih v il v il v il v ol v il v ih v hh v il v pplk v pph1/2/3 v ih v il addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) v pp (v) ry/by# (r) a in a in t avav t avwh t elwl t wheh t whgl t whwl t whqv1/2/3/4 t wlwh t dvwh t whdx valid srd t phwl t whrl t vpwh t qvvl d in d in high z d in t phhwh t qvph t whax (note 1) (note 2) (note 3) (note 4) (note 5) (note 6) notes : 1. v cc power-up and standby. 2. write block erase or word write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. fig. 12 ac waveform for we#-controlled write operations
lh28f800bg-l (for sop) - 33 - 6.2.6 alternative ce#-controlled writes (note 1) ?v cc = 2.7 to 3.6 v, t a = 0 to +70?c versions lh28f800bg-l85 lh28f800bg-l12 unit symbol parameter note min. max. min. max. t avav write cycle time 120 150 ns t phel rp# high recovery to ce# going low 2 1 1 s t wlel we# setup to ce# going low 0 0 ns t eleh ce# pulse width 70 70 ns t phheh rp# v hh setup to ce# going high 2 100 100 ns t vpeh v pp setup to ce# going high 2 100 100 ns t aveh address setup to ce# going high 3 50 50 ns t dveh data setup to ce# going high 3 50 50 ns t ehdx data hold from ce# high 5 5 ns t ehax address hold from ce# high 5 5 ns t ehwh we# hold from ce# high 0 0 ns t ehel ce# pulse width high 25 25 ns t ehrl ce# high to ry/by# going low 100 100 ns t ehgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, ry/by# high 2, 4 0 0 ns t qvph rp# v hh hold from valid srd, ry/by# high 2, 4 0 0 ns ?v cc = 3.30.3 v, t a = 0 to +70?c versions lh28f800bg-l85 lh28f800bg-l12 unit symbol parameter note min. max. min. max. t avav write cycle time 100 130 ns t phel rp# high recovery to ce# going low 2 1 1 s t wlel we# setup to ce# going low 0 0 ns t eleh ce# pulse width 70 70 ns t phheh rp# v hh setup to ce# going high 2 100 100 ns t vpeh v pp setup to ce# going high 2 100 100 ns t aveh address setup to ce# going high 3 50 50 ns t dveh data setup to ce# going high 3 50 50 ns t ehdx data hold from ce# high 5 5 ns t ehax address hold from ce# high 5 5 ns t ehwh we# hold from ce# high 0 0 ns t ehel ce# pulse width high 25 25 ns t ehrl ce# high to ry/by# going low 100 100 ns t ehgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, ry/by# high 2, 4 0 0 ns t qvph rp# v hh hold from valid srd, ry/by# high 2, 4 0 0 ns notes : 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase or word write. 4. v pp should be held at v pph1/2/3 (and if necessary rp# should be held at v hh ) until determination of block erase or word write success (sr.1/3/4/5 = 0 : on boot blocks, sr.3/4/5 = 0 : on parameter blocks and main blocks).
lh28f800bg-l (for sop) - 34 - symbol parameter note min. max. min. max. min. max. t avav write cycle time 85 90 120 ns t phel rp# high recovery to ce# 2111s going low t wlel we# setup to ce# going low 0 0 0 ns t eleh ce# pulse width 50 50 50 ns t phheh rp# v hh setup to ce# going high 2 100 100 100 ns t vpeh v pp setup to ce# going high 2 100 100 100 ns t aveh address setup to ce# going high 3404040ns t dveh data setup to ce# going high 3 40 40 40 ns t ehdx data hold from ce# high 5 5 5 ns t ehax address hold from ce# high 5 5 5 ns t ehwh we# hold from ce# high 0 0 0 ns t ehel ce# pulse width high 25 25 25 ns t ehrl ce# high to ry/by# going low 90 90 90 ns t ehgl write recovery before read 0 0 0 ns t qvvl v pp hold from valid srd, 2, 4 0 0 0 ns ry/by# high t qvph rp# v hh hold from valid srd, 2, 4 0 0 0 ns ry/by# high versions v cc 0.25 v v cc 0.5 v (note 5) lh28f800bg-l85 (note 6) lh28f800bg-l12 (note 6) lh28f800bg-l85 unit notes : 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase or word write. 4. v pp should be held at v pph1/2/3 (and if necessary rp# should be held at v hh ) until determination of block erase or word write success (sr.1/3/4/5 = 0 : on boot blocks, sr.3/4/5 = 0 : on parameter blocks and main blocks). 5. see fig. 8 "transient input/output reference waveform" and fig. 10 "transient equivalent testing load circuit" (high seed configuration) for testing characteristics. 6. see fig. 9 "transient input/output reference waveform" and fig. 10 "transient equivalent testing load circuit" (standard configuration) for testing characteristics. 6.2.6 alternative ce#-controlled writes (contd.) (note 1) ?v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c
lh28f800bg-l (for sop) - 35 - v il v ih v oh v ih v ih v ih v il v il v il v ol v il v ih v hh v il v pplk v pph1/2/3 v ih v il addresses (a) we# (w) oe# (g) ce# (e) data (d/q) rp# (p) v pp (v) ry/by# (r) a in a in t avav t aveh t wlel t ehwh t ehgl t ehel t ehqv1/2/3/4 t eleh t dveh t ehdx valid srd t phel t ehrl t vpeh t qvvl d in d in high z d in t phheh t qvph t ehax (note 1) (note 2) (note 3) (note 4) (note 5) (note 6) notes : 1. v cc power-up and standby. 2. write block erase or word write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. fig. 13 ac waveform for ce#-controlled write operations
lh28f800bg-l (for sop) - 36 - 6.2.7 reset operations rp# (p) v il v ih v oh v ih v oh v ol v il v ol ry/by# (r) ry/by# (r) rp# (p) v il (c) rp# rising timing v ih 2.7 v/3.3 v/5 v v il rp# (p) v cc (a) reset during read array mode (b) reset during block erase or word write t plph t plrh t plph t 235vph fig. 14 ac waveform for reset operation reset ac specifications (note 1) notes : 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase or word write operation is not executing, the reset will complete within 100 ns. 3. a reset time, t phqv , is required from the latter of ry/by# or rp# going high until outputs are valid. 4. when the device power-up, holding rp#-low minimum 100 ns is required after v cc has been in predefined range and also has been in stable there. v cc = 2.7 to 3.6 v v cc = 3.30.3 v v cc = 5.00.5 v symbol parameter note min. max. min. max. min. max. unit rp# pulse low time t plph (if rp# is tied to v cc , this 100 100 100 ns specification is not applicable) t plrh rp# low to reset during 2, 3 22 20 12 s block erase or word write v cc 2.7 v to rp# high t 235vph v cc 3.0 v to rp# high 4 100 100 100 ns v cc 4.5 v to rp# high
lh28f800bg-l (for sop) - 37 - 6.2.8 block erase and word write performance (note 3, 4) ?v cc = 2.7 to 3.6 v, t a = 0 to +70?c v pp = 2.7 to 3.6 v v pp = 5.00.5 v v pp = 12.00.6 v symbol parameter note min. typ. (note 1) max. min. typ. (note 1) max. min. typ. (note 1) max. unit 32 k-word 2 44.6 17.7 12.6 s t whqv1 word write block t ehqv1 time 4 k-word 2 45.9 26.1 24.5 s block 32 k-word 2 1.46 0.58 0.42 s block write block time 4 k-word 2 0.19 0.11 0.11 s block 32 k-word 2 1.14 0.61 0.51 s t whqv2 block erase block t ehqv2 time 4 k-word 2 0.38 0.32 0.31 s block t whrh1 word write suspend 78 68 67s t ehrh1 latency time to read t whrh2 erase suspend latency 18 22 11 14 11 14 s t ehrh2 time to read ?v cc = 3.30.3 v, t a = 0 to +70?c notes : 1. typical values measured at t a = +25?c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, not 100% tested. v pp = 3.30.3 v v pp = 5.00.5 v v pp = 12.00.6 v symbol parameter note min. typ. (note 1) max. min. typ. (note 1) max. min. typ. (note 1) max. unit 32 k-word 2 44 17.3 12.3 s t whqv1 word write block t ehqv1 time 4 k-word 2 45 25.6 24 s block 32 k-word 2 1.44 0.57 0.41 s block write block time 4 k-word 2 0.19 0.11 0.1 s block 32 k-word 2 1.11 0.59 0.5 s t whqv2 block erase block t ehqv2 time 4 k-word 2 0.37 0.31 0.3 s block t whrh1 word write suspend 67 57 56s t ehrh1 latency time to read t whrh2 erase suspend latency 16.2 20 9.6 12 9.6 12 s t ehrh2 time to read
lh28f800bg-l (for sop) - 38 - notes : 1. typical values measured at t a = +25?c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, not 100% tested. v pp = 5.00.5 v v pp = 12.00.6 v symbol parameter note min. typ. (note 1) max. min. typ. (note 1) max. unit t whqv1 word write time 32 k-word block 2 12.2 8.4 s t ehqv1 4 k-word block 2 18.3 17 s block write time 32 k-word block 2 0.4 0.28 s 4 k-word block 2 0.08 0.07 s t whqv2 block erase time 32 k-word block 2 0.46 0.39 s t ehqv2 4 k-word block 2 0.26 0.25 s t whrh1 word write suspend latency time to read 5 6 4 5 s t ehrh1 t whrh2 erase suspend latency time to read 9.6 12 9.6 12 s t ehrh2 6.2.8 block erase and word write performance (contd.) (note 3, 4) ?v cc = 5.0 v0.25 v, 5.00.5 v, t a = 0 to +70?c
lh28f800bg-l (for sop) - 39 - 7 ordering information lh28f800bgn t -l85 device density 800 = 8 m-bit access speed (ns) 85 : 85 ns (5.0 0.25 v), 90 ns (5.0 0.5 v), 100 ns (3.3 0.3 v), 120 ns (2.7 to 3.6 v) 12 : 120 ns (5.0 0.5 v), 130 ns (3.3 0.3 v), 150 ns (2.7 to 3.6 v) package n = 44-pin sop (sop044-p-0600) architecture b = boot block power supply type g = smartvoltage technology operating temperature = 0 to +70 c product line designator for all sharp flash products block locate option t = top boot b = bottom boot valid operational combinations v cc = 2.7 to 3.6 v v cc = 3.30.3 v v cc = 5.00.5 v v cc = 5.00.25 v option order code 50 pf load, 50 pf load, 100 pf load, 30 pf load, 1.35 v i/o levels 1.5 v i/o levels ttl i/o levels 1.5 v i/o levels 1 lh28f800bgn-xl85 120 ns 100 ns 90 ns 85 ns 2 lh28f800bgn-xl12 150 ns 130 ns 120 ns
packaging 13.2 16.0 1.27 44 _ 0.4 44 1 23 22 0.15 (14.4) 0.1 typ. 0.4 0.2 0.05 0.15 m 0.15 28.2 2.7 1.275 0.2 0.1 0.2 0.15 0.1 package base plane 44 sop (sop044-p-0600)

▲Up To Search▲

Price & Availability of LH28F800BG-L-FOR-SOP

	To Download LH28F800BG-L-FOR-SOP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .